1. Field of the Invention
The present invention relates to a pixel unit, and more particular, to a pixel unit capable of auto-compensating parasitic capacitances.
2. Description of the Related Art
FIG. 1a is a schematic diagram of a conventional pixel unit. The pixel unit 1 comprises a thin film transistor (TFT) 12 and a storage capacitor 14. The TFT 12 comprises a gate electrode 122 coupled to a gate line 16, a source electrode 124 coupled to a source line, and a drain electrode 126.
The gate electrode 122 is formed by a first metal layer and the source electrode 124 and the drain electrode 126 is formed by a second metal layer. When an region 128, formed by a semiconductor layer, is disposed between the first and the second metal layers, a parasitical capacitor CP is formed by the gate electrode 122, an overlapping region A, and the drain electrode 126, wherein the drain electrode 126 overlaps the gate electrode 122 in the overlapping region A. Another parasitical capacitor is additionally formed near the gate electrode 122, an overlapping region B, and the source electrode 124, wherein the source electrode 124 overlaps the gate electrode 122 in the overlapping region B.
FIG. 1b is an equivalent circuit for the conventional pixel unit shown in FIG. 1a. FIG. 1c is a timing diagram for the conventional pixel unit shown in FIG. 1a. During period t1, a logic level of a scan signal, which is received by the gate line 16, is changed from low to high, the TFT 12 is turned on, the storage capacitor 14 and a liquid crystal capacitor CLC begins charging according to a data signal of the source line 18, and the voltage of the liquid crystal capacitor CLC is charged to reach a voltage V1.
After period t1, the logic level of the scan signal is changed from high to low such that the TFT 12 is turned off and a voltage V14 stored in the storage capacitor 14 is equal to the voltage V1. Since the parasitical capacitor CP is generated between the gate electrode 122 and the drain electrode 126, the voltage V14 stored in the storage capacitor 14 is reduced ΔV from the voltage V1.
Since the voltage V14 and the voltage stored in the liquid crystal capacitor CLC represent a brightness of the pixel unit 1, when the voltage V14 is changed, the pixel unit 1 will display abnormal brightness. A conventional method of solving this problem controls the common voltage Vcom of a first electrode 22. When the voltage V14 stored in storage capacitor 14 reduces ΔV, the common voltage Vcom1 is reduced ΔV to a new common voltage Vcom2.
When manufacturing large size display panels, because the area of a mask region is insufficient to cover the display panel, the display panel is divided into various regions. Lithography technology comprising an exposure step, a developing step, an etching step, is then executed in each region.
When an alignment error occurs in any step, the area of the overlapping region A is changed such that a capacitance of the parasitical capacitor CP is also changed. Since pixel units in different regions are formed during different periods, capacitances of the parasitical capacitors CP in different pixel units are different.
When capacitances of parasitical capacitors CP in a display are different, the conventional solution cannot compensate effect for the effect upon parasitical capacitors.